Reconfigurable logic circuits, such as field-programmable gate arrays (FPGAs), and non-reconfigurable logic circuits, such as application-specific integrated circuits (ASICs), have many applications, including use in prototypes as well as end-products, and advantageously provide immediate, full-speed operation in prototype or pre-production form. The ability to debug such logic circuits in a real environment is very desirable.
Design verification systems, such as accelerators, simulators, and/or emulators, traditionally are used to provide emulation environments for developing logic circuits, including reconfigurable logic circuits and non-reconfigurable logic circuits. Such design verification systems include connector systems that, by their nature, are used with many different system configurations. For example, each system configuration can require different types of cable assemblies and/or subsystems to be coupled with the connector systems of the design verification systems. Each cable assembly and subsystem must be identified and/or verified to inhibit incorrect system configurations that can damage the design verification system, the cables, and the devices.
The connector systems of some commercially-available design verification systems are keyed to inhibit improper connection between the design verification systems and the cable assemblies and/or subsystems. Thereby, only one selected type of functional cable assembly typically is permitted to couple with each connector system. Other design verification systems include connector systems with dedicated identification pins for enabling selected specific functions. Since system users frequently are responsible for specifying the permitted usages of such connector systems, however, these design verification systems typically do not include any provisions for guaranteeing that the identification pins have been properly configured.
In view of the foregoing, a need exists for an improved design verification system that overcomes the aforementioned obstacles and deficiencies of currently-available design verification systems.